There’s an article about an announcement from Xilinx about its new ‘adaptive compute acceleration platform’. It’s at a marketing level, so I can’t fully understand what it’s saying.
It talks about “hardware adaptable” compute engines, and I am having a hard time figuring out how a chip could be “hardware adaptable”. That makes it sound like there is a physical switch that gets thrown somewhere. While microelectromechanical systems have done some amazing things, I have a hard time imagining physical switches on chips being worth the trouble.
Does anybody have any insight on this?